The past few years have seen a dramatic increase in the speed of data transmission capabilities among and between the various components of a computer system or between multiple computer systems connected together in a network configuration. Indeed, since the general acceptance of personal computer systems in the 1960's, data transmission speeds have grown with an almost power law dependence; about 1 MHz in the '60's, 10 MHz in the '70's, 100 MHz in the '80's, and 1 GHz speeds being routinely achieved in the '90's.
The development of optical fibre for transmission of digital data streams has become a particular enabling technology for modern day 1 GHz data transmission speeds and, in the computer industry, has given rise to a data transfer protocol and interface system termed Fibre-Channel. Fibre-Channel technology involves coupling various computer systems together with optical fibre or a fibre channel-type electrically conductive (copper) cable and allows extremely rapid data transmission speeds between machines separated by relatively great distances. However, because of the physical characteristics of fibre channel-type cable, present day systems are capable of serial-fashion data transmission (at least when only a single optical fibre or electrical cable is used to interconnect various computer systems). In contrast, computer systems are configured to almost universally handle data in parallel fashion on byte-multiple signal busses (8-bit, 16-bit or 32-bit busses), making it incumbent on any data transmission system to provide some means for converting a 1 GHz serial data stream into a byte or byte-multiple parallel data stream. Conversely, since the fibre channel protocol contemplates two-way data transmission, computer systems that typically operate with parallel data structures must have some means for serializing a byte or byte-multiple data stream into a 1 GHz data signal suitable for transmission down an optical fibre or an electrically conductive (copper) cable.
Parallel data being serialized for high speed transmission is typically synchronous, in that the sequence of 1's and 0's making up the resulting serial data stream occurs with reference to a synchronized, uniform, single-frequency serializer clock signal. Encoding and transmitting the clock signal, together with data, would necessarily require an inordinate amount of valuable serial bandwidth and reduce the overall data transmission speed of a fibre channel system. Even though some small degree of self-clocking is inherent in the serial data stream, some method of evaluating the data stream must be used in order that a transceiver or serial-to-parallel data recovery system may determine how to appropriately frame the binary data stream into bytes.
In accordance with the Fibre-Channel 10-bit Interface specification, amplified in ANSI X3.230-1994 document, an encoded byte is 10-bits in length and is referred to as a transmission character. Data provided over a typical computer system's parallel architecture must be encoded and framed such that each data byte (8-bits from the point of view of the computer system) is formed into a transmission character, often termed a Fibre Channel 8B/10B encoded character. The resulting 8B/10B character must then be transmitted as 10 sequential bits at a 1.06 GHz data rate in accordance with the interface specification. Likewise, an incoming 8B/10B encoded transmission character must be received at a 1.06 GHz data rate and converted (framed) into the encoded 10 bit byte.
In the receiver case, many systems perform this function by using various types of clock recovery circuits, the most common of which is a phase-lock loop, which generates or regenerates a synchronous timing reference signal from a serial data stream and provides the timing reference to a data synchronizer or deserializer in order to mark-in time, the anticipated occurrence of a serial data bit. In effect, a phase-lock loop generates a synchronous stream of successive timing references, each timing reference representing, for example, a bit cell with which a data bit may be associated. For example, 10 consecutive timing references might represent a framed 8B/10B Fibre Channel transmission character which might then be latched out onto a 10-bit parallel bus by a, for example, deserializer comprising a 10-bit counter. The phase-lock loop clock recovery circuit, accordingly, is an essential component in modern day GHz transceiver systems.
In like fashion, transmitter sections are configured to receive an 8B/10B encoded transmission character and convert the 10-bit byte into serial data and transmit the serialized data at a 1.06 GHz data rate.
The frequency of clock signals recovered by, for example, a receiver phase lock loop, is subject to a number of variations introduced by the electronic components of such systems. Typically, the electronic components in the data path introduce some elements of phase and frequency noise which are random in nature and, more particularly, have dramatically varying band width characteristics depending on the geometric and electronic variations in modern semiconductor manufacturing process parameters. A phase lock loop such as comprises a 1.06 GHz to 106 MHZ transceiver, must take these variations into account when attempting to deal with a 1.06 GHz serial data stream.
Implementations of such a transceiver, typically include at least a phase-locked loop (PLL) normally comprising a phase or phase and frequency detector, a charge pump, an analog filter, and some means for generating a synchronous clock signal, such as a voltage controlled oscillator (VCO).
During initialization, or power-on reset, during what is conventionally termed a frequency or velocity lock, the oscillation frequency of the VCO is determined by, and locked to, the frequency of an external clock provided for such purpose, just prior to receiving an incoming serial data stream. Once frequency or velocity lock is established, the VCO runs in what might be termed a quasi-flywheel mode at a mean frequency determined during velocity lock. Subsequent correction control to the VCO frequency is developed by phase-locking a transition edge of the synchronous VCO signal to a transition edge of the data ONE bits of an incoming serial data signal. The VCO is phase-locked to the incoming serial data stream by comparing the phase of the rising edge of the VCO clock signal to the phase of the rising edge of a data ONE bit, in a phase detector. Phase or time differences detected between the two rising edges causes a control signal to be issued to a charge pump which either pumps-up or pumps-down the VCO, thus directing the VCO to either speed up or slow down in response to frequency variation in the data stream.
An analog low pass filter is typically provided between the charge pump and the VCO to reject corrections resulting from random high-frequency variations of individual data bytes, and allow ideally only corrections resulting from consistent frequency shifts of the data stream. The VCO is therefore locked to the mean phase of the data stream rather than to the phase of a particular data bit. Once phase-locked, the synchronous VCO signal provides for a recovered clock signal whose rate (frequency) is equal to the data bit rate or an integral multiple thereof.
A particular shortcoming of phase lock loop systems used in conjunction with a GHz serial data receiver is that such phase lock loop systems may easily lose frequency or velocity lock in the event of an interruption to the serial data stream, the serial link itself or upon the occurrence of a data ZERO overrun. The Fibre-Channel Interface specification defines the serial data stream as comprising no more than five sequential 1's or 0's in accordance with the fibre-channel coding algorithm. A large number of sequential ZERO'S caused by either corrupted data or a loss of the serial link, results in there being no data leading edges with which to compare the phase of a VCO signal. The receiver phase lock loop thus, "flywheels" in an almost open-loop mode with the magnitude of the last correction provided to the VCO by the charge pump being retained in the system and causing the VCO frequency to continually increase or decrease in response. In typical prior art systems, the VCO frequency shift continues until the phase lock loop system loses lock which is typically defined as a frequency deviation greater than the "lock range". The lock range is necessarily dependent on the bandwidth of the phase lock loop system but is commonly expressed as either a percentage of the mean frequency or some fixed value about the mean frequency. In typical GHz data transmission systems, the lock range for a phase lock loop VCO operating at about 1.06 GHz is commonly taken to be +.backslash.-2.5% or approximately +.backslash.-25 MHz.
Since the operational frequency of a VCO corresponds to the control voltage V.sub.c, in a fashion well understood by those having skill in the art, typical prior art systems monitor the control voltage and define lock loss as a particular excursion (with either positive or negative polarity) of the control voltage beyond a nominal or median value. As a control voltage exceeds the lock threshold, a controller circuit (a microprocessor, microcontroller, digital signal processor, or the like) conventionally asserts an external signal termed lock reference or LCKREF which causes a receiver phase lock loop to enter frequency or velocity lock mode and reacquire lock.
As is well understood in the art, and which will be described in greater detail below, conventional receiver phase lock loop systems comprise alternate detector systems, a phase only detector operable in the data phase detection and deserializer mode, and a phase and frequency detector operable in response to an external synchronous clock (termed reference clock or REFCLK), by which the phase lock loop achieves velocity lock to a mean frequency corresponding to the mean frequency of the serial data stream. The LCKREF signal functions to switch the detection mode of the phase lock loop from phase only to phase and frequency detection during the assertion period of LCKREF. LCKREF is typically derived from an external timer and is asserted for a period of about 500 microseconds, following which LCKREF is deasserted and the PLL shifts from phase and frequency detection to phase only detection in anticipation of incoming data. Thus, upon loss of lock a phase lock loop has a period of about 500 microseconds in which to reacquire velocity lock prior to continuing its clock recover tasks.
It will be noted that, while effective in identifying lock loss and providing a means for velocity lock reacquisition, these prior art systems require an inordinate amount of time to reestablish proper operation following a frequency deviation beyond their lock ranges. For example, bit "jitter" and other random irregularities in the occurrence of a particular data ONE bit leading edge may cause a generally false, but ultimately correctable, phase lead or lag indication to a charge pump which sources or sinks a corresponding amount of current to or from a capacitor, in well known fashion, causing control changes to the VCO control voltage V.sub.c. The output frequency of the VCO is increased or decreased, as appropriate. If, however, the incoming data signal next comprises a string of data ZEROS which is subsequently interrupted for a brief period of time, this last error indication will remain impressed on the VCO control voltage and, if large enough, will cause the VCO frequency to very quickly exceed the lock range. This entire process may occur in a period of time as brief as 25 to 50 microseconds, following which the serial link may recover. However, having exceeded its lock range, the phase lock loop is pulled off-line for a period of at least 500 microseconds, during which it must reestablish velocity lock before again phase-locking to data. This 500 microsecond period during which a receiver phase lock loop is off-line represents a lifetime in the GHz environment and corresponds to the loss of vast amounts of data expressed in fibre channel transmission characters.
Moreover, even after having reacquired velocity lock, it is highly unlikely that the serial data stream can be correctly framed into the proper 10-bit transmission characters. Data bytes provided to follow on circuitry will necessarily be corrupted causing the system to abort the data transfer and signal for re-transmission. Accordingly, in addition to the 500 microsecond technical delay caused by velocity lock reacquisition, frequency deviations in excess of a PLL's lock range most often result in re-transmission with a consequent halving of the effective data transmission rate.
Accordingly, there is a demonstrated need for a phase lock loop system in which the frequency characteristics of a receiver phase lock loop (clock recovery circuit) is monitored and the receiver phase lock loop automatically reestablishes frequency lock as soon as the monitored VCO frequency is seen to deviate beyond the lock range. Such a phase lock loop should be able to reestablish lock without the intervention of any external processing circuitry and at speeds at least an order of magnitude faster than the conventional 500 microsecond time period imposed by LCKREF.